What can AI-powered test and measurement equipment enable semiconductor design engineers to do that previously took weeks?

A GPU chip trains an AI model for days on end, then suddenly returns wrong results without raising a single error. The cause is rarely the algorithm. It is a voltage droop lasting a few nanoseconds that ordinary instruments are too slow to see.

In next-generation semiconductor structures such as AI processing chips, wide bandgap SiC and GaN materials and high-speed data interfaces, a single test cycle can generate terabytes of waveform data and noise parameters. That volume has outgrown what any R&D team can read by eye or process by hand.

How do you catch the hidden fault that can bring down an entire AI model?

In AI data center infrastructure, GPU and NPU chips work with very large memory bandwidth through DDR5 and HBM, while moving data over standards such as PCIe Gen 6 and USB4v2. The chip runs at extreme current, high temperature and constant nanosecond switching. A single burst of Jitter or one very short voltage droop (Transient Power Droop) is enough to corrupt data silently. Engineers call this Silent Data Errors, and it can ruin an entire training session.

High-end oscilloscopes such as the Tektronix MSO Series 5B, 6B and DPO 7 Series handle this with intelligent measurement algorithms. The instrument automatically separates Random Jitter (RJ) from Deterministic Jitter (DJ). With that separation, engineers can tell whether a fault comes from the clock design, the power delivery network (PDN) or crosstalk on the PCB, without guessing and testing one hypothesis at a time.

How can compliance testing shrink from days to a few hours?

Before a chip can go into mass production (Tape-out), the R&D team must prove the product meets industry standards such as those from IEEE. Done by hand, this verification step often takes weeks. Tektronix KickStart and Clarius Compliance build test scripts automatically, align phase skew and calculate errors, so a repetitive procedure drops to a few hours.

The most notable part is the Eye Diagram. AI algorithms analyze Eye Width and Eye Height in real time at very low bit error rates (BER), in the range of 10⁻¹² to 10⁻¹⁵, then deliver a Pass or Fail verdict against international standards. Engineers no longer sit reading each diagram, and the chip reaches certification sooner on its way to market.

What does power testing for AI data centers and SiC, GaN semiconductors require?

Traditional silicon is giving way to wide bandgap materials such as SiC (Silicon Carbide) and GaN (Gallium Nitride). Higher efficiency comes with very demanding power requirements. AI infrastructure consumes enormous energy, so power stages must convert with high efficiency across a DC voltage range of 400V to 800V.

On the power source side, Tektronix offers the EA-ELR 21000 regenerative electronic load, used to simulate, test and analyze high-power supplies up to 800V for AI data centers and electric vehicles (EV). On the component side, Keithley SMU parameter analyzers combined with the IsoVu™ optically isolated probe measure static and dynamic characteristics such as I-V, C-V and Double Pulse Test. Engineers capture ultra-fast pulse signals and very high differential voltages without industrial noise corrupting the data.

Why is testing the deciding link for Vietnam's semiconductor industry?

Vietnam's semiconductor strategy centers on two core stages, integrated circuit design (IC Design) and testing with packaging (ATP, covering Assembly, Testing and Packaging). A Make in Vietnam chip can only go far when the country's testing capability meets international standards, because this stage decides R&D quality and the ability to join the global value chain.

So that engineers, researchers and local businesses can get hands-on with advanced test infrastructure, EMIN is partnering with Tektronix to host Tektronix Semiconductor Seminar 2026 under the theme Enabling Viet Nam’s Semiconductor Future. The event starts at 9:00 AM and ends at 2:00 PM on Wednesday, November 11, 2026, on the 6th floor of the NIC Hanoi building, 7 Ton That Thuyet Alley, Cau Giay, Hanoi.

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What is on the seminar agenda, and what do you get by attending?

The program has 4 technical presentations and 1 hands-on session.

1. Mr. Tan Chuan-Shin, Tektronix80 years of innovation in test and measurement, from the Transistor to AI.
2. Mr. Stephen Tang, TektronixTest solutions for wide bandgap SiC and GaN semiconductors, covering material research through detailed Failure Analysis.
3. Mr. Tan Chuan-Shin, TektronixDevice validation methods in the era of Physical AI.
4. Mr. Pho Duc Nam, Tektronix VietnamAdvanced research and education Lab infrastructure.
5. Live DemoOperate and measure hands-on with the MSO Series oscilloscope, Keithley SMU and next-generation AI power test equipment, right beside Tektronix experts.

The program is completely free and includes a tea break and a relaxed lunch, but seats are limited. If your work involves IC design, chip testing or power electronics, reserve your seat early so you do not miss this experience.